1. Field of the Invention
The present invention relates to methods for forming transistors and, more particularly, to methods for forming thin film transistors.
2. Description of the Related Art
Thin film electronics are particularly useful for large area electronics that can be made over non-planar and flexible substrates. Such applications limit the fabrication to optical lithography approaches. Thin film transistors (TFT) are the basic building blocks of large area electronic circuits such as those used in the backplanes of active matrix liquid crystal displays (AMLCD) of the type often used in flat panel monitors and televisions. In these applications, TFT based circuits are used to control the activation of pixels that make up the display. In some applications, thin film circuits are produced over non-planar surfaces and in other applications they are required to be optically transparent to the visible light. Yet in other applications, they are fabricated on flexible substrates. The conventional transistors made on single crystal substrates cannot be used in these unique applications.
Historically, TFTs have been made from amorphous silicon (a-Si) films to satisfy the application requirements described above, rather than the single crystal Si as it is the case with conventional electronic circuits such as the microprocessor circuits of contemporary computers. Transistors made from a-Si, however, suffer from a number of deficiencies including low electron mobility, light sensitive operation, limited switching ratios, low current density and poor threshold voltage uniformity. Other type of thin film transistors are made from organic semiconductors. However, these types of devices have even lower electron mobility, lower current densities and poorer threshold voltage control than a-Si. These known deficiencies of a-Si and organic TFTs make them unsuitable for the current generation of display circuit applications that demand higher switching speeds and threshold voltage accuracy.
In recent years, metal-oxide semiconductors have been considered for display electronics applications. Among several metal-oxide semiconductors that are useful for thin film applications, Zn, In, Sn, Ga, and Hf containing metal-oxides have shown good promise. One of the most promising metal-oxide semiconductor for thin film and transparent transistor applications is ZnO, which is transparent because of its wide band gap (3.4 eV), has high thin film electron mobility and can be easily prepared by several deposition techniques. ZnO and related composition thin film transistors have been shown to be suitable for high performance circuit applications beyond display electronics because of their superior electronic properties. These applications include microwave signal amplification, switching and mixing, high speed logic circuits and high speed control electronics. Other metal-oxide based thin film semiconductors are also useful when they are a mixed combination of several metal-oxides. For example, indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO) are ternary and quarternary compound semiconductors are being used.
The speed of thin film transistors relate directly to their gate length, which must be kept as short as possible to lower electron transport time between electrodes and improve its high frequency response characteristics. Since current density is proportional to W/L, where W is the gate width and L is the gate length, reduced gate length improves device current density capability. However, wavelength related limitations of optical lithography make it suitable only for line widths larger than 1 micrometer. Advanced and costly lithography techniques involving electron beams, phase shift techniques etc. are generally not compatible with large area electronics. These advanced lithography techniques applied to contemporary single crystal microelectronics rely on extremely well controlled substrate surface flatness and photoresist uniformity. These conditions cannot generally be maintained for thin film electronics and, therefore, large gate lengths (i.e. source-drain spacing), are typically used in thin film transistors, which limit the electronic speed of circuits to lower frequencies. This is especially true for metal oxide TFTs, whose fabrication technology maturity is less than a-Si. Additionally, short channel transistors are also useful for low voltage operation but suffer from high output conductance characteristics if the channel is uniformly doped. And, high output conductivity limits the power gain obtainable from such devices.
In a bottom gate TFT 10, as shown schematically in FIG. 1, a first layer to be fabricated on a substrate 12 is a conductive gate metal 14. Other layers are fabricated over this layer in sequence during fabrication. Unwanted portions of each layer are removed by etching while protecting the portions of the layer with protective films such as photoresist. The most critical dimension that influences the device performance is the distance between the source 16 and the drain electrodes 18. This distance is the effective channel 20 length, as shown in FIG. 1. The composition and doping level of a semiconductor layer 22 within this channel 20 are normally kept uniform.
The gap between source 16 and drain 18 electrodes can be produced by several techniques including “lift-off” and etching. In the lift-off technique, photoresist patterns are fabricated by opening areas in the resist corresponding to the electrodes. These areas are filled with evaporated metal. Excess metal over the photoresist is removed when it is dissolved in solvent. In the etching technique, the metal layer is first produced over the entire surface by for example sputtering techniques. Photoresist patterns are then produced over the metal layer to mask areas that correspond to the electrodes. The unprotected metal surfaces are etched until all metal in these areas are removed. It is important that the etchant used to remove the metal layer does not also etch the semiconductor layer or damage its surface. In either approach, the critical dimension is the gate length. As set out above, using photolithography, the minimum gate length that can be produced is about twice the wavelength of the light used to expose the photoresist. High speed metal oxide TFTs using this technique have about 1 micrometer gate lengths. Similar size gate lengths were achieved for amorphous Si based TFTs as described in “Method of Manufacturing Semiconductor Device,” U.S. Pat. No. 7,537,979 by Isobe et al.
An alternative photolithography-based fabrication method was described in “Method of Fabricating a TFT with Reduced Channel Length,” U.S. Pat. No. 5,532,180 by den Boer et al. and ““TFT with Reduced Channel Length and Parasitic Capacitance,” U.S. Pat. No. 5,872,370 by Gu et al. In this approach, the source and drain electrodes are fabricated separately. By relying on positioning accuracy of the equipment, these transistor electrodes were placed closer to each other than the optical resolution of the photolithography tool. However, these approaches introduce an additional process step which can be a source of additional surface damage to the semiconductor layer. Also, the positioning approach may introduce alignment errors in both X and Y dimensions so that across the wafer there may be rotational misalignments. The minimum gate length sizes were limited to 1-4 micrometers due to these restrictions.
Other short-channel thin film transistor fabrication methods were described in “Vertical Thin Film Transistor with Short-Channel Effect Suppression,” U.S. Pat. No. 7,629,633 by Chan et al. and “Method of Making a High Performance Small Area Thin Film Transistor,” U.S. Pat. No. 4,543,320 by Vijan using vertical channels. Rather than relying on lithography techniques to implement a lateral separation between source and gate electrodes, this method relies on separating the source and drain electrodes vertically by stacking them and providing an insulating layer between them. Since the vertical dimensions are more easily controlled than lateral dimensions, the method can produce channel lengths smaller than a micrometer. However, the actual transistor is fabricated along the sidewalls of the contacts in substantially the vertical direction. Control of channel quality along the vertical direction is typically more challenging than the conventional horizontal surfaces.
Shorter gate lengths may also be fabricated using expensive lithography techniques such as “Leading-edge KrF Scanner” technique with special photoresists, near-field lithography, nanoimprint technology, and electron beam lithography. Although, these sophisticated lithography techniques are slow, expensive and generally not compatible with the thin film electronics produced over large area substrates.
What is needed in the art, therefore, is a method of fabricating short gate length thin film transistors without the limitations or difficulties associated with contemporary fabrication methods.